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MTV10N100E - TMOS POWER FET 10 AMPERES 1000 VOLTS

Key Features

  • OSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used.

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Full PDF Text Transcription (Reference)

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www.DataSheet4U.com MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTV10N100E/D Designer's TMOS E-FET .™ Power Field Effect Transistor D 3 PAK for Surface Mount N–Channel Enhancement–Mode Silicon Gate The D3PAK package has the capability of housing the largest chip size of any standard, plastic, surface mount power semiconductor. This allows it to be used in applications that require surface mount components with higher power and lower RDS(on) capabilities. This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage–blocking capability without degrading performance over time. In addition, this advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes.