NXP Semiconductors BS208
P-channel enhancement mode vertical D-MOS transistor
| Part No. | BS208 |
|---|---|
| Datasheet | BS208 Download |
| Manufacturer |  NXP Semiconductors |
| Description | P-channel enhancement mode vertical D-MOS transistor |
| Buy | Stock & Price |
FEATURES
● Direct interface to C-MOS● High-speed switching
● No secondary breakdown.
DESCRIPTION
P-channel enhancement mode vertical D-MOS transistor in a TO-92 envelope. Intended for use in relay, high-speed and line transformer drivers. PINNING - TO-92 PIN 1 2 3DESCRIPTION
source gate drain MAM149 BS208 handbook, halfpage 1 d 2 3 g s Fig.1 Simplified outline and symbol. QUICK REFERENCE DATA SYMBOL VDS VGSO Yfs ID RDS(on) Ptot PARAMETER drain-source voltage (DC) gate-source voltage (DC) forward transfer admittance drain current (DC) drain-source on-state resistance VGS = −10 V; ID = −200 mA total power dissipation Tamb = 25 °C open drain ID = −200 mA; VDS = −25 V CONDITIONS − − 100 − − − MIN. − − 200 − 10 − TYP. MAX. −200 ±20 − −0.2 14 0.83 V V mS A Ω W UNIT April 1995 2 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134) SYMBOL −VDS ±VGSO −ID −IDM Ptot Tstg Tj P...
