PHB21N06LT Datasheet | NXP Semiconductors

FEATURES - ’Trench’ technology - Low on-state resistance - Fast switching - Logic level patible g PHP21N06LT, PHB21N06LT PHD21N06LT QUICK REFERENCE DATA d SYMBOL VDSS = 55 V ID = 19 A RDS(ON) ≤ 75 mΩ (VGS = 5 V) RDS(ON) ≤ 70 mΩ (VGS = 10 V) s GENERAL DESCRIPTION N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. Applications:- d.c. to d.c. converters - switched mode power supplies The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB21N06LT is supplied in the SOT404 (D2PAK) surface mounting package. The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package. PINNING PIN 1 2 3 tab DESCRIPTION gate drain 1 source SOT78 (TO220AB) tab SOT404 (D2PAK) tab SOT428 (DPAK) tab 1 23 3 drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS VGSM ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Pulsed gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ Tj ≤ 150˚C Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 55 55 ± 15 ± 20 19 13 76 56 175 UNIT V V V V A A A W ˚C 1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages. August 1999 1 Rev 1.500 Philips Semiconductors Product specification N-channel Trench MOS™ transistor Logic level FET AVALANCHE ENERGY LIMITING VALUES PHP21N06LT, PHB21N06LT PHD21N06LT Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy Peak non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 9.7 A; tp = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 25 V; RGS = 50 Ω; VGS = 5 V; refer to fig:15 MIN. MAX. 34 UNIT m J - 19 THERMAL...