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SC18IS601 - SPI to IC-bus interface

This page provides the datasheet information for the SC18IS601, a member of the SC18IS600 SPI to IC-bus interface family.

Datasheet Summary

Description

The SC18IS600/601 is designed to serve as an interface between the standard SPI of a host (microcontroller, microprocessor, chip set, etc.) and the serial I2C-bus.

This allows the host to communicate directly with other I2C-bus devices.

Features

  • I I I I I I I SPI slave interface SPI Mode 3 Master I2C-bus controller General Purpose Input/Output (GPIO) pins: 4 (SC18IS600); 3 (SC18IS601) Two quasi-bidirectional I/O pins 5 V tolerant I/O pins High-speed SPI: N Up to 3 Mbit/s (SC18IS601) N Up to 1.2 Mbit/s (SC18IS600) High-speed I2C-bus: 400 kbit/s 96-byte transmit buffer 96-byte receive buffer 2.4 V to 3.6 V operation Power-down mode with WAKEUP pin Oscillator: internal (SC18IS600); external (SC18IS601) Active LOW interrupt output Available.

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Datasheet preview – SC18IS601

Datasheet Details

Part number SC18IS601
Manufacturer NXP
File Size 527.64 KB
Description SPI to IC-bus interface
Datasheet download datasheet SC18IS601 Datasheet
Additional preview pages of the SC18IS601 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com SC18IS600/601 SPI to I2C-bus interface Rev. 03 — 13 December 2006 Product data sheet 1. General description The SC18IS600/601 is designed to serve as an interface between the standard SPI of a host (microcontroller, microprocessor, chip set, etc.) and the serial I2C-bus. This allows the host to communicate directly with other I2C-bus devices. The SC18IS600/601 can operate as an I2C-bus master-transmitter or master-receiver. The SC18IS600/601 controls all the I2C-bus specific sequences, protocol, arbitration and timing. The key distinction between the SC18IS600 and the SC18IS601 lies in the clock source: internal (SC18IS600) versus external (SC18IS601). 2.
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