NT5CB128M8FN - 1Gb SDRAM

Datasheet Summary

The 1Gb Double-Data-Rate-3 (DDR3(L)) F-die DRAMs is double data rate architecture to achieve high-speed operation.

It is internally configured as an eight bank DRAM.

The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 banks or 8Mbit x 16 I/Os x 8 bank devices.

JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
Power Saving Mode - Partial Array Self Refresh (PASR)1 - Power Down Mode.
Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (2.

Nanya

Part number	NT5CB128M8FN
Manufacturer	Nanya
File Size	3.20 MB
Description	1Gb SDRAM
Datasheet	NT5CB128M8FN Datasheet
Additional preview pages of the NT5CB128M8FN datasheet.

Other Datasheets by Nanya

Click to expand full text

DDR3(L) 1Gb SDRAM NT5CB(C)128M8FN / NT5CB(C)64M16FP Nanya Technology Corp.

Published: Feb 24, 2015 |