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NT5CB128M8FN - 1Gb SDRAM

General Description

The 1Gb Double-Data-Rate-3 (DDR3(L)) F-die DRAMs is double data rate architecture to achieve high-speed operation.

It is internally configured as an eight bank DRAM.

The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 banks or 8Mbit x 16 I/Os x 8 bank devices.

Key Features

  • JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
  • Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
  • Power Saving Mode - Partial Array Self Refresh (PASR)1 - Power Down Mode.
  • Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (2.

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Datasheet Details

Part number NT5CB128M8FN
Manufacturer Nanya
File Size 3.20 MB
Description 1Gb SDRAM
Datasheet download datasheet NT5CB128M8FN Datasheet

Full PDF Text Transcription for NT5CB128M8FN (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for NT5CB128M8FN. For precise diagrams, and layout, please refer to the original PDF.

DDR3(L) 1Gb SDRAM NT5CB(C)128M8FN / NT5CB(C)64M16FP Nanya Technology Corp....

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