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NT5CB128M8GN - Industrial and Automotive DDR3(L) 1Gb SDRAM

Download the NT5CB128M8GN datasheet PDF. This datasheet also covers the NT5CC128M8GN variant, as both devices belong to the same industrial and automotive ddr3(l) 1gb sdram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Basis DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
  • Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
  • Power Saving Mode - Partial Array Self Refresh (PASR)1 - Power Down Mode.
  • Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (2.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (NT5CC128M8GN-Nanya.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number NT5CB128M8GN
Manufacturer Nanya
File Size 3.51 MB
Description Industrial and Automotive DDR3(L) 1Gb SDRAM
Datasheet download datasheet NT5CB128M8GN Datasheet

Full PDF Text Transcription for NT5CB128M8GN (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for NT5CB128M8GN. For precise diagrams, and layout, please refer to the original PDF.

NTC Proprietary Level: Property DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP Commercial, Industrial and Automotive DDR3(L) 1Gb SDRAM Features  Basis DDR3 Complian...

View more extracted text
strial and Automotive DDR3(L) 1Gb SDRAM Features  Basis DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM  Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes  Power Saving Mode - Partial Array Self Refresh (PASR)1 - Power Down Mode  Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%)  Signal Synchronization - Write Leveling via MR settings 6 - Read Leveling via MPR 

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