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CD4013BC - Dual D Flip-Flop

Download the CD4013BC datasheet PDF. This datasheet also covers the CD4013BM variant, as both devices belong to the same dual d flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The CD4013B dual D flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors Each flip-flop has independent data set reset and clock inputs and ‘‘Q’’ and ‘‘Q’’ outputs These devices can be used for shift register applications

Key Features

  • Y Wide supply voltage range Y High noise immunity Y Low power TTL compatibility 3 0V to 15V 0 45 VDD (typ ) fan out of 2 driving 74L or 1 driving 74LS.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CD4013BM_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CD4013B CMOS Dual D-type Flip-Flop RCA
CD4013B CMOS Dual D-Type Flip-Flop Texas Instruments
CD4013BMS CMOS Dual D-Type Flip-Flop Intersil Corporation
CD4013A CMOS Dual D-type Flip-Flop RCA
CD40100B CMOS 32-Stage Static Left/Right Shift Register RCA

Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
CD4013BM Dual D Flip-Flop
CD40106BC Hex Schmitt Trigger
CD40106BM Hex Schmitt Trigger
CD4010C Hex Buffers
CD4010M Hex Buffers

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CD4013BM CD4013BC Dual D Flip-Flop February 1988 CD4013BM CD4013BC Dual D Flip-Flop General Description The CD4013B dual D flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors Each flip-flop has independent data set reset and clock inputs and ‘‘Q’’ and ‘‘Q’’ outputs These devices can be used for shift register applications and by connecting ‘‘Q’’ output to the data input for counter and toggle applications The logic level present at the ‘‘D’’ input is transferred to the Q output during the positive-going transition of the clock pulse Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line respectively Features Y Wide supply voltage range Y High noise imm