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DS90CF363A - +3.3V Programmable LVDS Transmitter

Datasheet Summary

Description

The DS90C363A/DS90CF363A transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link.

Features

  • n 20 to 65 MHz shift clock support n Rejects > ± 3ns Jitter from VGA chip with less than 225ps output Jitter @65MHz (TJCC) n Best.
  • in.
  • Class Set & Hold Times on TxINPUTs n Tx power consumption < 130 mW (typ) @65MHz Grayscale n > 50% Less Power Dissipation than BiCMOS Alternatives n Tx Power-down mode < 200µW (max) n ESD rating > 7 kV (HBM), > 500V (EIAJ) n Supports VGA, SVGA, XGA and Dual Pixel SXGA. n Narrow bus reduces cable size and cost n Up to 1.3 Gbps throughput n Up to 170 M.

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Datasheet Details

Part number DS90CF363A
Manufacturer National Semiconductor
File Size 219.56 KB
Description +3.3V Programmable LVDS Transmitter
Datasheet download datasheet DS90CF363A Datasheet
Additional preview pages of the DS90CF363A datasheet.

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Full PDF Text Transcription

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DS90C363A/DS90CF363A +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD)Link-65 MHz June 1998 DS90C363A/DS90CF363A +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz +3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz General Description The DS90C363A/DS90CF363A transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted.
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