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DS90CF384A - +3.3V LVDS Receiver

This page provides the datasheet information for the DS90CF384A, a member of the DS90-CF384 +3.3V LVDS Receiver family.

Datasheet Summary

Description

The DS90CF384A receiver converts the four LVDS data streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL).

Features

  • n n n n n n n n n n n 20 to 65 MHz shift clock support 50% duty cycle on receiver output clock Best.
  • in.
  • Class Set & Hold Times on RxOUTPUTs Rx power consumption < 142 mW (typ) @65MHz Grayscale Rx Power-down mode < 200µW (max) ESD rating > 7 kV (HBM), > 700V (EIAJ) Supports VGA, SVGA, XGA and Dual Pixel SXGA. PLL requires no external components Compatible with TIA/EIA-644 LVDS standard Low profile 56-lead or 48-lead TSSOP package DS90CF384A is also available in a 64 ball, 0.8mm fin.

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www.DataSheet4U.com DS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit-Color Flat Panel Display (FPD) Link—65 MHz , +3.3V LVDS Receiver 18-Bit-Color Flat Panel Display (FPD) Link—65 MHz February 2006 DS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link—65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link—65 MHz General Description The DS90CF384A receiver converts the four LVDS data streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF364A that converts the three LVDS data streams (Up to 1.
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