DS99R101 Overview
The DS99R101/DS99R102 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector...
DS99R101 Key Features
- 3 MHz-40 MHz clock embedded and DC-Balancing 24:1
- User selectable clock edge for parallel data on both
