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DS99R101 - (DS99R101 / DS99R102) 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Description

The DS99R101/DS99R102 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.

Features

  • es.
  • 3 MHz.
  • 40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions Transmitter and Receiver.
  • User selectable clock edge for parallel data on both coupling interface with no external coding required Individual power-down controls for both Transmitter and Receiver Embedded clock CDR (clock and data recovery) on Receiver and no external source of reference clock needed All codes RDL (random data lock) to support livepluggable.

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Datasheet Details

Part number DS99R101
Manufacturer National Semiconductor
File Size 938.07 KB
Description (DS99R101 / DS99R102) 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
Datasheet download datasheet DS99R101 Datasheet
Additional preview pages of the DS99R101 datasheet.

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Full PDF Text Transcription

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DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer October 2007 www.DataSheet4U.com DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description The DS99R101/DS99R102 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. The DS99R101/DS99R102 incorporates LVDS signaling on the high-speed I/O.
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