P5504EDG - P-Channel Logic Level Enhancement

This page provides the datasheet information for the P5504EDG, a member of the P5504EDG_Niko P-Channel Logic Level Enhancement family.

Niko-Sem

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Datasheet Details

Part number	P5504EDG
Manufacturer	Niko-Sem
File Size	409.47 KB
Description	P-Channel Logic Level Enhancement
Datasheet	P5504EDG Datasheet
Additional preview pages of the P5504EDG datasheet.

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Full PDF Text Transcription

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NIKO-SEM P-Channel Enhancement Mode Field Effect Transistor P5504EDG TO-252 Halogen-Free & Lead-Free D PRODUCT SUMMARY V(BR)DSS -40V RDS(ON) 55mΩ ID -21A G S 1. GATE 2. DRAIN 3. SOURCE ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Power Dissipation 1 SYMBOL VDS VGS LIMITS -40 ±20 -21 -13 -39 41 16 -55 to 150 UNITS V V TC = 25 °C TC = 100 °C ID IDM A TC = 25 °C TC = 100 °C PD Tj, Tstg W °C Operating Junction & Storage Temperature Range THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Case Junction-to-Ambient 1 SYMBOL RθJC RθJA TYPICAL MAXIMUM 3 75 UNITS °C / W °C / W Pulse width limited by maximum junction temperature.

Published: Dec 30, 2010 |