Datasheet Summary
Low Skew Output Buffer
Features
Frequency range 75 ~ 180MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).
- Zero input
- output delay.
- Less than 700 ps device
- device skew.
- Less than 250 ps skew between outputs. ..
- Less than 150 ps cycle
- cycle jitter.
- Output Enable function tri-state outputs.
- 3.3V operation.
- Available in 8-Pin 150mil SOIC GREEN package.
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PIN CONFIGURATION
REF CLK2 CLK1 GND
1 2 3 4
8 7 6 5
CLKOUT CLK4 VDD CLK3
Remark
If REF clock is stopped for more than 10us after it has already been provided to the chip, and after...