PLL102-108 - Programmable DDR Zero Delay Clock Driver

Product Overview

PhaseLink Corporation

Datasheet Details

Part number	PLL102-108
Manufacturer	PhaseLink Corporation
File Size	198.33 KB
Description	Programmable DDR Zero Delay Clock Driver
Datasheet	PLL102-108 Datasheet
Additional preview pages of the PLL102-108 datasheet.

Product details

Description

The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output.

Features

PLL clock distribution optimized for Double Data Rate SDRAM.

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Other Datasheets by PhaseLink Corporation

PLL102-10 - Low Skew Output Buffer
PLL102-109 - Programmable DDR Zero Delay Clock Driver
PLL102-15 - Low Skew Output Buffer
PLL102-03 - Low Skew Output Buffer
PLL102-04 - Low Skew Output Buffer
PLL102-05 - Low Skew Output Buffer

Published: Oct 28, 2008 |