Datasheet Details
| Part number | PLL102-108 |
|---|---|
| Manufacturer | PhaseLink Corporation |
| File Size | 198.33 KB |
| Description | Programmable DDR Zero Delay Clock Driver |
| Datasheet | PLL102-108_PhaseLinkCorporation.pdf |
|
|
Overview: PLL102-108 Programmable DDR Zero Delay Clock Driver.
| Part number | PLL102-108 |
|---|---|
| Manufacturer | PhaseLink Corporation |
| File Size | 198.33 KB |
| Description | Programmable DDR Zero Delay Clock Driver |
| Datasheet | PLL102-108_PhaseLinkCorporation.pdf |
|
|
|
S The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output.
Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT.
The PLL can be bypassed for test purposes by strapping AV dd to ground.
| Part Number | Description |
|---|---|
| PLL102-10 | Low Skew Output Buffer |
| PLL102-109 | Programmable DDR Zero Delay Clock Driver |
| PLL102-15 | Low Skew Output Buffer |
| PLL102-03 | Low Skew Output Buffer |
| PLL102-04 | Low Skew Output Buffer |
| PLL102-05 | Low Skew Output Buffer |
| PLL103-01 | Low Skew Buffer |
| PLL103-02 | DDR SDRAM Buffer |
| PLL103-03 | DDR SDRAM Buffer |
| PLL103-04 | 1-to-4 Clock Distribution Buffer |