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PLL102-15 Datasheet Low Skew Output Buffer

Manufacturer: PhaseLink Corporation

Overview: PLL102-15 Low Skew Output Buffer.

General Description

S The PLL102 -15 is a high performance, low skew, low jitter zero delay buffer designed to di stribute high speed clocks and is available in 8 -pin SOIC or TSSOP package.

It has four outputs that are synchronized with the input.

The synchronization is established via CLKOUT feedback to the input of the PLL.

Key Features

  • Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation).
  • Zero input - output delay.
  • Less than 700 ps device - device skew.
  • Less than 250 ps skew between outputs. www. DataSheet4U. com.
  • Less than 200 ps cycle - cycle jitter.
  • Output Enable function tri -state outputs.
  • 3.3V operation.
  • Available in 8 -Pin 150mil SOIC.

More Datasheets from PhaseLink Corporation

Part Number Description
PLL102-10 Low Skew Output Buffer
PLL102-108 Programmable DDR Zero Delay Clock Driver
PLL102-109 Programmable DDR Zero Delay Clock Driver
PLL102-03 Low Skew Output Buffer
PLL102-04 Low Skew Output Buffer
PLL102-05 Low Skew Output Buffer
PLL103-01 Low Skew Buffer
PLL103-02 DDR SDRAM Buffer
PLL103-03 DDR SDRAM Buffer
PLL103-04 1-to-4 Clock Distribution Buffer

PLL102-15 Distributor