PLL130-09 Datasheet | PhaseLink Corporation

FEATURES - - - - - Differential LVDS output Single AC coupled input (min. 100m V swing). Input range from DC to 1.0 GHz. 2.5V to 3.3V operation. Available in 8-Pin SOIC or 3x3mm QFN. PIN CONFIGURATION (TOP VIEW) GND REF_IN 1 2 3 4 8 7 6 5 VDD GND LVDS_BAR VDD .. DESCRIPTION The PLL130-09 is a low cost, high performance, high speed, buffer that reproduces any input frequency from DC to 1.0GHz. It provides a pair of differential LVDS output. Any input signal with at least 100m V swing can be used as reference signal. This chip is ideal for conversion from sine wave, TTL, CMOS, or PECL to LVDS. GND LVDS GND GND GND OE^ 13 14 15 16 8 7 6 5 LVDS_BAR VDD LVDS GND 1 2 3 4 REF_IN Note: ^ denotes internal pull up BLOCK DIAGRAM REF_IN Input LVDS_BAR LVDS Amplifier 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 .phaselink. Rev 09/09/04 Page 1 High Speed Translator Buffer to LVDS PIN DESCRIPTIONS Name GND VDD REF_IN .. 8pin SOIC Pin number 1,3,7 5,8 2 4 7 N/A 3x3mm QFN Pin...