Description
The HY[I/B]39S512[40/80/16]0A[E/T] are four bank Synchronous DRAM’s organized as 4 banks × 32MBit ×4, 4 banks × 16MBit ×8 and 4 banks × 8Mbit ×16 respectively.
Features
- e e t 4 U . c o m
This chapter lists all main features of the product family HY[I/B]39S512[40/80/16]0A[E/T] and the ordering information. 1.1.
- Fully Synchronous to Positive Clock Edge 0 to 70 °C Operating Temperature for HYB -40 to 85 °C Operating Temperature for HYI Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2 & 3 Programmable Wrap Sequence: Sequential or Interleave Programma.
HYI39S512160A Datasheet
