Download the HYI39S512400A datasheet PDF.
This datasheet also covers the HYI39S512160A variant, as both devices belong to the same 512-mbit synchronous dram family and are provided as variant models within a single manufacturer datasheet.
General Description
The HY[I/B]39S512[40/80/16]0A[E/T] are four bank Synchronous DRAM’s organized as 4 banks × 32MBit ×4, 4 banks × 16MBit ×8 and 4 banks × 8Mbit ×16 respectively.
Key Features
e e t 4 U . c o m
This chapter lists all main features of the product family HY[I/B]39S512[40/80/16]0A[E/T] and the ordering information. 1.1.
Fully Synchronous to Positive Clock Edge 0 to 70 °C Operating Temperature for HYB -40 to 85 °C Operating Temperature for HYI Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2 & 3 Programmable Wrap Sequence: Sequential or Interleave Programma.
Full PDF Text Transcription for HYI39S512400A (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
HYI39S512400A. For precise diagrams, and layout, please refer to the original PDF.
June 2007 HY[B/I]39S512400A[E/T] HY[B/I]39S512800A[E/T] HY[B/I]39S512160A[E/T] www.DataSheet4U.com 512-Mbit Synchronous DRAM SDRAM RoHS Compliant Products Internet Data S...
View more extracted text
12-Mbit Synchronous DRAM SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.52 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM HY[B/I]39S512400A[E/T], HY[B/I]39S512800A[E/T], HY[B/I]39S512160A[E/T] Revision History: 2007-06, Rev. 1.52 Page All 13 www.DataSheet4U.com 13 15 19 21 Subjects (major changes since last revision) Adapted internet edition Corrected operation command "Power Down / Clock suspend ...” in truth table Corrected operation command "Power Down Exit" to X (WE#) Corrected text to "After the mode register is set a NOP command is required" , chapter 3.3 Corrected text to "One
HYI39S512400A Datasheet
