HYI39S512800A Datasheet | Qimonda

Overview D a t a S h Features e e t 4 U . c o m This chapter lists all main features of the product family HY[I/B]39S512[40/80/16]0A[E/T] and the ordering information. 1.1. - - - - - - - - - - Fully Synchronous to Positive Clock Edge 0 to 70 °C Operating Temperature for HYB... -40 to 85 °C Operating Temperature for HYI... Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2 & 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 and full page Multiple Burst Read with Single Write Operation Automatic and Controlled Precharge mand Data Mask for Read / Write control (x4, x8, x16) - - - - - - - - - Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 8192 refresh cycles / 64 ms (7.8 µs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plastic Package : P(G)-TSOPII-54 Ro HS pliant product TABLE 1 Performance Product Type Speed Code Speed Grade Max. Clock Frequency @CL3 - 7.5 PC133- 333 1) Unit - MHz ns ns ns ns @CL2 1) Max. Frequency CL/t RCD / t RP f CK3 t CK3 t AC3 t CK2 t AC2 133 7.5 5.4 10 6 Rev. 1.52, 2007-06 03292006-6Y91-0T2Z Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM Description The HY[I/B]39S512[40/80/16]0A[E/T] are four bank Synchronous DRAM’s organized as 4 banks × 32MBit ×4, 4 banks × 16MBit ×8 and 4 banks × 8Mbit ×16 respectively. These synchronous devices achieve high speed data transfer rates for CAS...