Datasheet Details
| Part number | HYI39SC128160FE |
|---|---|
| Manufacturer | Qimonda |
| File Size | 1.15 MB |
| Description | 128-MBit Synchronous DRAM |
| Datasheet |
 HYI39SC128160FE Datasheet
|
|
|
General Description
output circuits are synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs.
Key Features
- Data Mask for Read / Write control (×8) Data Mask for Byte Control (×16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 µs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plastic Packages: PG.
- TSOPII.
- 54 400 mil width This chapter lists all main features of the product family HY[B/I]39S128[8.