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HYI39SC128800FE - 128-MBit Synchronous DRAM

Product Overview

Qimonda

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HYI39SC128800FE 128-MBit Synchronous DRAM by Qimonda - Datasheet Preview — Datasheet preview – HYI39SC128800FE

Datasheet Details

Part number	HYI39SC128800FE
Manufacturer	Qimonda
File Size	1.15 MB
Description	128-MBit Synchronous DRAM
Datasheet	HYI39SC128800FE Datasheet
Note	This datasheet PDF includes multiple part numbers: HYI39SC128800FE, HYI39SC128160FE. Please refer to the document for exact specifications by model.
Additional preview pages of the HYI39SC128800FE datasheet.

Product details

Description

output circuits are synchronized with the positive edge of an externally supplied clock.

Features

Data Mask for Read / Write control (×8) Data Mask for Byte Control (×16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 µs) Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface Plastic Packages: PG.
TSOPII.
54 400 mil width This chapter lists all main features of the product family HY[B/I]39S128[8.

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Published: Sep 10, 2008 |