SLG47004 Datasheet | Renesas

Features General Description The SLG47004 provides a small, low power ponent for monly used analog signal processing and mixed-signal functions. Individual, tunable, analog ponents used in conjunction with configurable logic provide a way to solve a wide variety of tasks with minimal costs. The user creates their circuit design by programming the multiple time Non-Volatile Memory (NVM) to configure the interconnect logic, the analog and digital macrocell, and the IO Pins of the SLG47004. Key Features - Two Programmable Bandwidth Op Amps - 3-Op Amp Instrumentation Amplifier Function (including Additional Internal Op Amp) - Rail to Rail Input - Low Quiescent Current - Low Offset Voltage - Analog parator Mode - Optional Vref Voltage Connection for Input Pins - Two 1024 Position Digital Rheostats - User Defined Auto-Trim Option - Manual Control Option - I2C Control Option - Potentiometer Mode - Two Single-Pole/Single-Throw Analog Switches - Voltage or Current Source/Sink Mode - One Low Offset Chopper parator - Two Low Power General Purpose ACMPs - ACMP Sampling Mode - Hysteresis with Independently-Selectable Thresholds - Three Voltage References - Two ACMP Vref Output Buffers - One High Drive Buffer - Thirteen bination Function Macrocells - Three Selectable DFF/LATCH or 2-bit LUTs - One Selectable Programmable Pattern Generator or 2-bit LUT - Seven Selectable DFF/LATCH or 3-bit LUTs - One Selectable Pipe Delay or Ripple Counter or 3-bit LUT - One Selectable DFF/LATCH or 4-bit LUT - Seven Multi-Function Macrocells - Six Selectable DFF/LATCH or 3-bit LUTs + 8-bit Delay/Counters - One Selectable DFF/LATCH or 4-bit LUT + 16-bit Delay/Counter - Serial munications - I2C Protocol Interface - 2-kbit (256 x 8) I2C-patible (2-Wire) Serial EEPROM Emulation with Software Write Protection - Programmable Delay with Edge Detector...