SLG47011 Datasheet | Renesas

Features - SAR ADC - 14-, 12-, 10-, 8-bit Selectable Resolution - Up to 2.35 Msps in 8-bit mode - Sampling up to Four Analog Channels - Output Options: Parallel, I2C, SPI - Programmable Gain Amplifier - 1x to 64x Gain Selection - Differential, Single-Ended Modes - Math Core - Multiplier, Adder, Subtractor, Shifter Options - Four Independent Data Buffers - Buffer Length up to Eight 16-bit Words - Oversampling Mode (Increasing ADC Resolution) - Moving Average Mode - Counter Capture Mode - 4096 Words x 12-bit Memory Table Macrocell - Full Range Mode or Two Ranges Mode - ADC Data Linearization or Any y = F(x) Function - ADDR-to-DATA/Storage Modes - 16-bit Multichannel Digital parator (MDCMP) - Sampling up to Four Independent Channels - Static or Dynamic Threshold - Hysteresis Option for Each Channel - PWM Macrocell - 12-bit Resolution - Dynamic Duty Cycle Change (up to 4096 Duty Cycle Value) - Width Converter Macrocell - 12-bit Parallel Data Output - Optional 12 x 1-bit, 6 x 2-bit, 3 x 4-bit Output - 12-bit 333 ksps Digital-to-Analog Converter - Selectable Current Source - Integrated Voltage References (VREF) - High Speed Analog parator - Configurable Hysteresis and Reference - Eighteen bination Function Macrocells - Two 2-bit LUT or DFF/LATCH Macrocells - Eight 3-bit LUT or DFF/LATCH with Set/Reset - Six Selectable DFF/LATCH or 3-bit LUTs or Shift Registers - Two 4-bit LUT or DFF/LATCH with Set/Reset...