SLG47105 Datasheet | Renesas

Features General Description The SLG47105 provides a small, low power ponent for monly used Mixed-Signal and Bridge functions. The user creates their circuit design by programming the one time programmable (OTP) Non-Volatile Memory (NVM) to configure the interconnect logic, the IO Pins, the High Voltage Pins, and the macrocells of the SLG47105. Configurable PWM macrocells in bination with Special High Voltage outputs will be useful for a motor drive or load drive applications. High Voltage pins allow to design smart level translators or to drive the high voltage high current load. Key Features - Two Power Supply Inputs: - 2.5 V (±8 %) to 5.0 V (±10 %) VDD - 3.3 V (±9 %) to 12.0 V (±10 %) VDD2 - Four High Voltage High Current Drive GPOs - Dual/Single Full Bridge Driver Option - Quad/Dual/Single Half Bridge Driver Option - Slew Rate Modes: - Motor Driver Mode - Pre-Driver (MOSFET Driver) Mode - SLEEP Function - Low RDS ON High Side + Low Side resistance = 0.4  - 2 A Peak, 1.5 A RMS per Full Bridge (at VDD2 = 5 V, T = 25 °C) (Note 1) - 4 A Peak, 3 A RMS per two Full Bridge connected in parallel (at VDD2 = 5 V, T = 25 °C) (Note 1) - 2 A Peak, 1.5 A RMS per Half Bridge GPO (at VDD2 = 5 V, T = 25 °C) (Note 1) - Integrated Protections: - Over Current Protection (OCP) - Short Circuit Protection - Under-Voltage Lockout (UVLO) - Thermal Shutdown (TSD) - SENSE_A, SENSE_B Inputs that are connected to the Current parators for Current Control - Fault Signal Indicator individual per Full Bridge: - OCP - UVLO - TSD - Differential Amplifier with Integrator and parator for Motor Speed Control Function - Two Current Sense parators with Dynamical Vref Mode - Two High-Speed General Purpose ACMPs - Modes: UVLO, OCP, TSD, Voltage Monitor, Current Monitor - One Voltage Reference (Vref) Output - Five Multi-Function Macrocells - Four Selectable DFF/LATCH/3-bit LUTs + 8-bit Delay/ Counters - One Selectable DFF/LATCH/4-bit LUT + 16-bit Delay/ Counter - Twelve bination Function Macrocells - Three...