SLG47115 Datasheet | Renesas

Features The SLG47115 provides a small, low power ponent for monly used Mixed-Signal and Full Bridge functions. The user creates their circuit design by programming the one time programmable (OTP) Non Volatile Memory (NVM) to configure the interconnect logic, the IO Pins, the High Voltage Pins, and the macrocells of the SLG47115. Configurable PWM macrocells in bination with Special High Voltage outputs will be useful for a motor drive or load drive applications. High Voltage pins allow to design smart level translators or to drive the high voltage high current load. Features - Two Power Supply Inputs: - 2.5 V (±8 %) to 5.0 V (±10 %) VDD - 5.0 V (±10 %) to 24.0 V (±10 %) VDD2 - Two High Voltage High Current Drive GPOs - Full Bridge Driver Option - Dual/Single Half Bridge Driver Option - Slew Rate Modes: ◦ Motor Driver Mode ◦ Pre-Driver (MOSFET Driver) Mode - High Drive GPOs with Sleep Function - Low RDS(ON) High-side + Low-side resistance = 0.5 typical - 3 A Peak, 1.5 A RMS per Full Bridge[1] - Current up to 3 A Peak, 1.5 A RMS per GPO/Half Bridge and up to 6 A Peak, 3 A RMS for two HV GPOs Connected in Parallel[1] - Integrated Over Current/Short Circuit/Undervoltage-Lockout Protections - SENSE Input that is connected to the Current parator for Current Control - Fault Signal Indicator (OCP/UVLO/TSD/) - Differential Amplifier with Integrator and parator for Motor Speed Control Function - Current Sense parator with Dynamical Vref Mode - Two High-Speed General Purpose ACMPs - Modes: UVLO, OCP, TSD, Voltage Monitor, Current Monitor - One Voltage Reference (Vref) Output - Five Multi-Function Macrocells - Four Selectable DFF/LATCH/3-bit LUTs + 8-bit Delay/Counters - One Selectable DFF/LATCH/4-bit LUT + 16-bit Delay/Counter - Twelve bination Function Macrocells - Three Selectable DFF/LATCH or 2-bit LUTs - One Selectable Programmable Pattern Generator or 2-bit LUT - Six Selectable DFF/LATCH or 3-bit LUTs - One Selectable Pipe Delay or Ripple Counter or 3bit...