SLG47910 Datasheet | Renesas

Description The SLG47910 is a small size, low power ponent for mon FPGA applications. The user creates their circuit design by writing RTL Verilog or using the graphical mode to configure the interconnections, logic blocks, and input/output pins of the SLG47910. This highly versatile device allows a wide variety of FPGA applications to be designed. Features - Dense Array of Configurable Logic - 1120 5-bit Look-Up Tables (LUTs) - 1120 D-type Flip Flops (DFFs) - 5 kb distributed Static Random-Access Memory (SRAM) - 32 kb embedded SRAM (BRAM) - Configurable through onboard NVM and/or SPI interface - 50 MHz On-chip Oscillator (OSC) - Phase-Locked Loop (PLL) - Clock from external source or internal Oscillator - Power Supply - VDDIO: 1.71 V to 3.465 V - VDDC: 1.1 V ± 5 % - Power-On-Reset (POR) - General Purpose Input Output (GPIO) Count - 19 GPIOs + 2 GPIs in STQFN Packaging - Configuration Modes - Internal One-Time Programmable (OTP) Non- Volatile Memory (NVM) - External SPI Flash Memory with power-down option - External SPI Microcontroller (MCU) - Maximum Configuration Bitstream Security (OTP Mode) - Reset and Low Power Sleep Functionality with data retention (GPO, FPGA Core, BRAMs) - Operating Temperature Range: -40 °C to +85 °C - Ro HS pliant/Halogen-Free Package - 24-pin STQFN: 3.0 mm x 3.0 mm x 0.55 mm, 0.4 mm pitch Applications - Consumer Electronics - Data munications Equipment - Handheld and Portable Electronics - Notebooks and Tablet PCs - Industrial Applications R19DS0120EU0104 Rev 1.04 Feb 25, 2025 Page 1 © 2025 Renesas Electronics SLG47910 Datasheet Contents Description...