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K7B401825B - 128Kx36/x32 & 256Kx18 Synchronous SRAM

General Description

The K7B163625A and K7B161825A are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

Key Features

  • Synchronous Operation.
  • On-Chip Address Counter.
  • Self-Timed Write Cycle.
  • On-Chip Address and Control Registers.
  • 3.3V+0.165V/-0.165V Power Supply.
  • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
  • 5V Tolerant Inputs Except I/O Pins.
  • Byte Writable Function.
  • Global Write Enable Controls a full bus-width write.
  • Power Down State via ZZ Signal.
  • LBO Pin allows.

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Full PDF Text Transcription for K7B401825B (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K7B401825B. For precise diagrams, and layout, please refer to the original PDF.

K7B163625A K7B161825A Document Title 512Kx36 & 1Mx18 Synchronous SRAM 512Kx36 & 1Mx18-Bit Synchronous Burst SRAM Revision History Rev. No. 0.0 0.1 0.2 History 1. Initial ...

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s Burst SRAM Revision History Rev. No. 0.0 0.1 0.2 History 1. Initial draft 1. Add JTAG Scan Order 1. Add x32 org and industrial temperature . 2. Add 165FBGA package 1. Final spec release 1. Delete 119BGA package. 2. Correct the Ball Size of 165 FBGA. 1. Delete x32 Org. 2. Delete 165FBGA package. 3. Delelte the 6.5 ns speed bin. Draft Date Feb. 23. 2001 May. 10. 2001 Aug. 30. 2001 Remark Preliminary Preliminary Preliminary 1.0 1.1 May. 10. 2002 April 04. 2003 Final Final 2.0 Nov. 17, 2003 Final -1- Nov. 2003 Rev 2.0 K7B163625A K7B161825A 512Kx36 & 1Mx18 Synchronous SRAM 16Mb SB/SPB Synchronous SRAM Ordering Information Org

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