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K7B403225B - 128Kx36/x32 & 256Kx18 Synchronous SRAM

This page provides the datasheet information for the K7B403225B, a member of the K7B 128Kx36/x32 & 256Kx18 Synchronous SRAM family.

Datasheet Summary

Description

The K7A403600B, K7A403200B and K7A401800B are 4,718,592-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

Features

  • Synchronous Operation.
  • 2 Stage Pipelined operation with 4 Burst.
  • On-Chip Address Counter.
  • Self-Timed Write Cycle.
  • On-Chip Address and Control Registers.
  • VDD= 3.3V+0.3V/-0.165V Power Supply.
  • VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
  • 5V Tolerant Inputs Except I/O Pins.
  • Byte Writable Function.
  • Global Write Enable Controls a full bus-width write.
  • P.

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Datasheet preview – K7B403225B

Datasheet Details

Part number K7B403225B
Manufacturer Samsung semiconductor
File Size 470.43 KB
Description 128Kx36/x32 & 256Kx18 Synchronous SRAM
Datasheet download datasheet K7B403225B Datasheet
Additional preview pages of the K7B403225B datasheet.

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Full PDF Text Transcription

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K7A403600B K7A403200B K7A401800B Document Title 128Kx36/x32 & 256Kx18 Synchronous SRAM 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No 0.0 0.1 History 1. Initial draft 1. Changed DC parameters Icc ; from 350mA to 290mA at -16, from 330mA to 270mA at -15, from 300mA to 250mA at -14, ISB1 ; from 100mA to 80mA 1. Delete Pass-Through 1. Add x32 org. and industrial temperature 1. Final spec release 2. Changed Pin Capacitance - Cin ; from 5pF to 4pF - Cout ; from 7pF to 6pF Draft Date May. 15. 2001 June. 12. 2001 Remark Preliminary Preliminary 0.2 0.3 1.0 June.25. 2001 Aug. 11. 2001 Nov. 15. 2001 Preliminary Preliminary Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD.
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