K7B403625M Datasheet | Samsung Semiconductor

Document Title 128Kx36-Bit Synchronous Burst SRAM 128Kx36 Synchronous SRAM Revision History Rev. No. History Draft Date 0.0 Initial draft May. 15. 1997 0.1 Modify power down cycle timing & Interleaved read timing, Insert Note 4 at AC timing characteristics. Change ISB1 value from 10m A to 30m A. Change ISB2 value from 10m A to 20m A. Feb. 11. 1998 0.2 Change Undershoot spec from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤t CYC/2) Add Overshoot spec 4.6V((pulse width≤t CYC/2) Change VIH max from 5.5V to VDD+0.5V April. 14. 1998 0.3 Change ISB2 value from 20m A to 30m A. May. 13. 1998 Change VDD condition from VDD=3.3V+10%/-5% to VDD=3.3V+0.3V/-0.165V. 1.0 Final spec Release May. 15. 1998 2.0 Add VDDQ Supply voltage( 2.5V ) Dec. 02. 1998 Remark Preliminary Preliminary Preliminary Preliminary Final Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications....