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K7J161882B - (K7J161882B / K7J163682B) 512Kx36 & 1Mx18 DDR II SIO b2 SRAM

General Description

Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Address Inputs Data Inputs 1 NOTE Q0-35 Data Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Input Refere

Key Features

  • 1.8V+0.1V/-0.1V Power Supply.
  • DLL circuitry for wide output data valid window and future freguency scaling.
  • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O.
  • Separate independent read and write data ports.
  • HSTL I/O.
  • Synchronous pipeline read with self timed late write.
  • Registered address, control and data input/output.
  • Full data coherency, providing most current data.
  • DDR(Double.

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Full PDF Text Transcription for K7J161882B (Reference)

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K7J163682B K7J161882B www.DataSheet4U.com Document Title 512Kx36 & 1Mx18 DDR II SIO b2 SRAM 512Kx36-bit, 1Mx18-bit DDR II SIO b2 SRAM Revision History Rev. No. 0.0 0.1 0....

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bit, 1Mx18-bit DDR II SIO b2 SRAM Revision History Rev. No. 0.0 0.1 0.2 0.3 History 1. Initial document. 1. Change the JTAG Block diagram 1. Add the speed bin (-25) 1. Correct the JTAG ID register definition 2. Correct the AC timing parameter (delete the tKHKH Max value) 1. Change the Maximum Clock cycle time. 2. Correct the 165FBGA package ball size. 1. Add the power up/down sequencing comment. 2. Update the DC current parameter (Icc and Isb). 3. Change the Max. speed bin from -33 to -30. 1. Change the ISB1. Speed Bin -30 -25 -20 -16 1.0 2.0 1. Final spec release 1. Delete the x8 Org. 2. Delete the 300MHz speed bin 1. Add

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