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K4D261638 - 128Mbit GDDR SDRAM

General Description

The K4D261638F is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology.

Key Features

  • 2.5V + 5% power supply for device operation.
  • 2.5V + 5% power supply for I/O interface.
  • SSTL_2 compatible inputs/outputs.
  • 4 banks operation.
  • MRS cycle with address key programs -. Read latency 3, 4 and 5(clock) -. Burst length (2, 4 and 8) -. Burst type (sequential & interleave).
  • All inputs except data & DM are sampled at the positive going edge of the system clock.
  • Differential clock input.
  • No Wrtie-Interrupted by Read Func.

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Full PDF Text Transcription for K4D261638 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K4D261638. For precise diagrams, and layout, please refer to the original PDF.

K4D261638F 128M GDDR SDRAM 128Mbit GDDR SDRAM 2M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM Revision 1.2 January 2004 Samsung Electronics reserves the ri...

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ous DRAM Revision 1.2 January 2004 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.2 (Jan. 2004) K4D261638F Revision History Revision 1.2 (January 30, 2004) • Changed tWR & tWR_A of K4D261638F-TC25/2A/33/36 from 3tCK to 4tCK • Changed tRC of K4D261638F-TC25 from 17tCK to 18tCK • Changed tRC of K4D261638F-TC2A/33/36 from 15tCK to 16tCK • Changed tRAS of K4D261638F-TC25 from 12tCK to 13tCK. • Changed tRAS of K4D261638F-TC2A/33/36 from 10tCK to 11tCK. • Changed tDAL of K4D261638F-TC25/2A/33/36 from 8tCK to 9tCK 128M GDDR SDRAM Revision 1.1 (January 7, 2004) • Added K4D26

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