K4D263238A Overview
K4D263238A-GC 128M DDR SDRAM 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL (144-Ball FBGA) Revision 2.0 January 2003 Samsung Electronics reserves the right to change products or specification without notice. Changed tCK(max) of K4D263238A-GC33/36 from 5ns to 4ns. For all the CL5 operation, guaranteed tCK(max) is 4ns.
K4D263238A Key Features
- 2.5V + 5% power supply for device operation
- 2.5V + 5% power supply for I/O interface
- SSTL_2 patible inputs/outputs
- 4 banks operation
- MRS cycle with address key programs -. Read latency 3,4,5 (clock) -. Burst length (2, 4, 8 and Full page) -. Burst type
- Full page burst length for sequential burst type only
- Start address of the full page burst should be even
- All inputs except data & DM are sampled at the positive going edge of the system clock
- Differential clock input
- No Wrtie-Interrupted by Read Function
