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K4D551638F-TC - 256Mbit GDDR SDRAM

General Description

The K4D551638F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology.

Key Features

  • 2.6V + 0.1V power supply for device operation.
  • 2.6V + 0.1V power supply for I/O interface.
  • SSTL_2 compatible inputs/outputs.
  • 4 banks operation.
  • MRS cycle with address key programs -. Read latency 3 (clock) -. Burst length (2, 4 and 8) -. Burst type (sequential & interleave).
  • All inputs except data & DM are sampled at the positive going edge of the system clock.
  • Differential clock input.
  • No Write-Interrupted by Read Function.

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Full PDF Text Transcription for K4D551638F-TC (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K4D551638F-TC. For precise diagrams, and layout, please refer to the original PDF.

Target Spec K4D551638F-TC 256M GDDR SDRAM 256Mbit GDDR SDRAM 4M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM Revision 1.7 June 2004 Samsung Electronics res...

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a Rate Synchronous DRAM Revision 1.7 June 2004 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev 1.7 (June 2004) Target Spec K4D551638F-TC Revision History Revision 1.7 (June 15, 2004) - Target Spec • Changed VDD/VDDQ of K4D551638F-TC33 from 2.8V + 0.1V to 2.8V(min)/2.95V(max) 256M GDDR SDRAM Revision 1.6 (March 31, 2004) - Target Spec • AC Changes : Refer to the AC characteristics of page 13 and 14. Revision 1.5 (March 18, 2004) - Target Spec • Added K4D551638F-TC33 in the data sheet. Revision 1.4 (February 27, 2004) - Target Spec • Added K4D551638F-TC36/40 in the data sh

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