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K4D553238F-JC - 256Mbit GDDR SDRAM

Description

The K4D553238F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology.

Features

  • 2.5V + 5% power supply for device operation.
  • 2.5V + 5% power supply for I/O interface.
  • SSTL_2 compatible inputs/outputs.
  • 4 banks operation.
  • MRS cycle with address key programs -. Read latency 3, 4 (clock) -. Burst length (2, 4 and 8) -. Burst type (sequential & interleave).
  • All inputs except data & DM are sampled at the positive going edge of the system clock.
  • Differential clock input.
  • No Wrtie-Interrupted by Read Function.

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Datasheet preview – K4D553238F-JC

Datasheet Details

Part number K4D553238F-JC
Manufacturer Samsung
File Size 297.43 KB
Description 256Mbit GDDR SDRAM
Datasheet download datasheet K4D553238F-JC Datasheet
Additional preview pages of the K4D553238F-JC datasheet.

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Full PDF Text Transcription

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K4D553238F-JC 256M GDDR SDRAM 256Mbit GDDR SDRAM 2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL (144-Ball FBGA) Revision 1.0 March 2004 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev 1.0 (Mar. 2004) K4D553238F-JC Revision History Revision 1.0 (March 8, 2004) • DC Specification finalized 256M GDDR SDRAM Revision 0.1 (March 2 , 2004) - Target Spec Revision 0.0 (October 28, 2003) - Target Spec • Defined Target Specification - 2 - Rev 1.0 (Mar. 2004) K4D553238F-JC 256M GDDR SDRAM 2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES • 2.5V + 5% power supply for device operation • 2.
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