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K4D623238B-GC - 64Mbit DDR SDRAM

Description

The K4D623238 is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 2 x1,048,976 words by 32 bits, fabricated with SAMSUNG ’ s high performance CMOS technology.

Features

  • 2.5V + 5% power supply for device operation.
  • VDD/VDDQ = 2.8V ± 5% for -33.
  • VDD/VDDQ = 2.5V ± 5% for -60/-55/-50/-45/-40.
  • SSTL_2 compatible inputs/outputs.
  • 4 banks operation.
  • MRS cycle with address key programs -. Read latency 3,4,5 (clock) -. Burst length (2, 4, 8 and Full page) -. Burst type (sequential & interleave).
  • Full page burst length for sequential burst type only.
  • Start address of the full page burst should be even.

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Datasheet preview – K4D623238B-GC

Datasheet Details

Part number K4D623238B-GC
Manufacturer Samsung
File Size 147.36 KB
Description 64Mbit DDR SDRAM
Datasheet download datasheet K4D623238B-GC Datasheet
Additional preview pages of the K4D623238B-GC datasheet.

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Full PDF Text Transcription

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K4D623238B-GC 64M DDR SDRAM 64Mbit DDR SDRAM 512K x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL (144-Ball FBGA) Revision 1.4 September 2002 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.4 (Sep. 2002) K4D623238B-GC Revision History Revision 1.4 (September 26, 2002) • Added tCK(min) and tCK(max) at CL=3 and CL=4 64M DDR SDRAM Revision 1.3 (March 5, 2002) • Changed tCK(max) of K4D623238B-GC40 from 7ns to 10ns. Revision 1.2 (September 1, 2001) • Added K4D623238B-GL* as a low power part (ICC6=1mA) • Added ICC7 (Operating current at 4bank interleaving) • Added 100MHz@CL2 Revision 1.1 (August 2, 2001) • Changed tCK(max) of K4D623238B-GC45/-50/-55/-60 from 7ns to 10ns. Revision 1.
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