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LH531024 - CMOS 1M (64K x 16) MROM

General Description

The LH531024 is a mask-programmable ROM organized as 65,536 × 16 bits.

It is fabricated using silicon-gate CMOS process technology.

Key Features

  • 65,536 words × 16 bit organization.
  • Access time: 100 ns (MAX. ).
  • Power consumption: Operating: 412.5 mW (MAX. ) Standby: 550 µW (MAX. ).
  • Static operation.
  • TTL compatible I/O.
  • Three-state outputs.
  • Single +5 V power supply.
  • JEDEC standard EPROM pinout (DIP).
  • Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP 44-pin, 650-mil QFJ (PLCC).

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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LH531024 FEATURES • 65,536 words × 16 bit organization • Access time: 100 ns (MAX.) • Power consumption: Operating: 412.5 mW (MAX.) Standby: 550 µW (MAX.) • Static operation • TTL compatible I/O • Three-state outputs • Single +5 V power supply • JEDEC standard EPROM pinout (DIP) • Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP 44-pin, 650-mil QFJ (PLCC) DESCRIPTION The LH531024 is a mask-programmable ROM organized as 65,536 × 16 bits. It is fabricated using silicon-gate CMOS process technology.