LH5316P00B Datasheet | Sharp Corporation

FEATURES - 2,097,152 × 8 bit organization (Byte mode: BYTE = VIL) 1,048,576 × 16 bit organization (Word mode: BYTE = VIH) - Access time: 120 ns (MAX.) - Supply current: - Operating: 70 m A (MAX.) - Standby: 100 µA (MAX.) - TTL patible I/O - Three-state output - Single +5 V power supply - Static operation - Package: 44-pin, 600-mil SOP - Item related with CO regulation: - Non programmable - Not designed or rated as radiation hardened - CMOS process (P type silicon substrate) DESCRIPTION The LH5316P00B is a 16M-bit mask-programmable ROM organized as 2,097,152 × 8 bits (Byte mode) or 1,048,576 × 16 bits (Word mode) that can be selected by a BYTE input pin. It is fabricated using silicon-gate CMOS process technology. CMOS 16M (2M × 8/1M × 16) MROM PIN CONNECTIONS 44-PIN SOP TOP VIEW NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE D0 D8 D1 D9 D2 D10 D3 D11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND D15/A-1 (NOTE) D7 D14 D6 D13 D5 D12 D4 VCC NOTE: The D15/A-1 pin bees LSB address input (A-1) when the BYTE pin is set to be LOW in byte mode and data output (D15) when set to be HIGH in word mode. The input state of BYTE pin can not be changed during operation. The BYTE pin must be set to either GND or VCC. 5316P00B-1 Figure 1. Pin Connections CMOS 16M (2M x 8/1M x 16) MROM A19 43 A18 2 A17 3 A16 34 A15 35 ADDRESS DECODER A14 36 A13 37 A12 38 A11 39 A10 40 A9 41 A8 42 A7 4 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 MEMORY MATRIX (2,097,152 x 8) (1,048,576 x 16) DATA SELECTOR/OUTPUT BUFFER ADDRESS BUFFER 31 29 27 25 D15 D14 D13 D12 22 D11 20 D10 18 D9 16 D8 30 D7 28 D6 26 24 21 19 17 15 D5 D4 D3 D2 D1 D0 COLUMN SELECTOR CE 12 CE BUFFER TIMING GENERATOR SENSE AMPLIFIER OE 14 OE...