TC58NVG1S3BFT00 Datasheet | Toshiba

w m INTEGRATED CIRCUIT SILICON GATE CMOS o TENTATIVE TOSHIBA MOS DIGITAL .c U × 16 BIT) CMOS NAND E2PROM 2 GBIT (256M × 8 BIT/128M 4 t DESCRIPTION e e h S a at .D w w Features - Organization Memory cell array Register Page size Block size - - TC58NVG1S3B 2112 × 128K × 8 2112 × 8 2112 bytes (128K + 4K) bytes TC58NVG1S8B 1056 × 128K × 16 1056 × 16 1056 words (64K + 2K) words TC58NVG1S3BFT00/TC58NVG1S8BFT00 The TC58NVG1Sx B is a single 3.3 V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes/(1024 + 32) words × 64 pages × 2048 blocks. The device has a 2112-byte/1056-word static register which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages). The TC58NVG1Sx B is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for mand inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. Modes Read, Reset, Auto Page Program, Auto Block Erase- C Status Read Mode control Serial input/output mand control Number of valid blocks Max 2048 blocks Min 2008 blocks Power supply VCC = 2.7 V to 3.6 V Program/Erase Cycles 100000 Cycles (With ECC) Access time Cell array to register Serial Read Cycle Program/Erase time Auto Page Program Auto Block Erase Operating current Read (50 ns cycle) Program (avg.) Erase (avg.) Standby - - - - - - w w w 25 µs max 50 ns min t a .D S a e h U 4 t e .c m o 200 µs/page typ. 1.5 ms/block typ. 10 m A typ. 10 m A typ. 10 m A typ. 50 µA max - Package TC58NVG1S3BFT00 TSOP I 48-P-1220-0.50 TC58NVG1S8BFT00 TSOP I...