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TC58NVG1S3BFT00 - 2-GBit CMOS NAND EPROM

General Description

e e h S a at .D w w

Key Features

  • Organization Memory cell array Register Page size Block size.
  • TC58NVG1S3B 2112 × 128K × 8 2112 × 8 2112 bytes (128K + 4K) bytes TC58NVG1S8B 1056 × 128K × 16 1056 × 16 1056 words (64K + 2K) words TC58NVG1S3BFT00/TC58NVG1S8BFT00 The TC58NVG1SxB is a single 3.3 V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes/(1024 + 32) words × 64 pages × 2048 blocks. The device has a 2112-byte/105.

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Full PDF Text Transcription for TC58NVG1S3BFT00 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for TC58NVG1S3BFT00. For precise diagrams, and layout, please refer to the original PDF.

w m INTEGRATED CIRCUIT SILICON GATE CMOS o TENTATIVE TOSHIBA MOS DIGITAL .c U × 16 BIT) CMOS NAND E2PROM 2 GBIT (256M × 8 BIT/128M 4 t DESCRIPTION e e h S a at .D w w FEA...

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PROM 2 GBIT (256M × 8 BIT/128M 4 t DESCRIPTION e e h S a at .D w w FEATURES • Organization Memory cell array Register Page size Block size • • TC58NVG1S3B 2112 × 128K × 8 2112 × 8 2112 bytes (128K + 4K) bytes TC58NVG1S8B 1056 × 128K × 16 1056 × 16 1056 words (64K + 2K) words TC58NVG1S3BFT00/TC58NVG1S8BFT00 The TC58NVG1SxB is a single 3.3 V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes/(1024 + 32) words × 64 pages × 2048 blocks. The device has a 2112-byte/1056-word static register which allow program and read data to be transferred betwe

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