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TC58NVG1S3ETA00 - 2 GBIT (256M x 8 BIT) CMOS NAND E2PROM

General Description

The TC58NVG1S3E is a single 3.3V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 2048blocks.

Key Features

  • Organization Memory cell array Register Page size Block size.
  • x8 2112 × 128K × 8 2112 × 8 2112 bytes (128K + 4K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read Mode control Serial input/output Command control Number of valid blocks Min 2008 blocks Max 2048 blocks Power supply VCC = 2.7V to 3.6V Access time Cell array to register Serial Read Cycle Program/Erase time A.

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Datasheet Details

Part number TC58NVG1S3ETA00
Manufacturer Toshiba
File Size 550.27 KB
Description 2 GBIT (256M x 8 BIT) CMOS NAND E2PROM
Datasheet download datasheet TC58NVG1S3ETA00 Datasheet

Full PDF Text Transcription for TC58NVG1S3ETA00 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for TC58NVG1S3ETA00. For precise diagrams, and layout, please refer to the original PDF.

TC58NVG1S3ETA00 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 GBIT (256M × 8 BIT) CMOS NAND E PROM DESCRIPTION The TC58NVG1S3E is a single 3.3V 2 Gbit (2,214...

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NAND E PROM DESCRIPTION The TC58NVG1S3E is a single 3.3V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 2048blocks. The device has two 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages). The TC58NVG1S3E is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command i

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