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TC58NYG2S3ETA00 - 4 GBIT (512M x 8 BIT) CMOS NAND E2PROM

General Description

The TC58NYG2S3E is a single 1.8V 4 Gbit (4,429,185,024 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 4096blocks.

Key Features

  • Organization Memory cell array Register Page size Block size x8 2112 × 256K × 8 2112 × 8 2112 bytes (128K + 4K) bytes.
  • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read.
  • Mode control Serial input/output Command control.
  • Number of valid blocks Min 4016 blocks Max 4096 blocks.
  • Power supply VCC = 1.7V to 1.95V.
  • Access time Cell array to.

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Datasheet Details

Part number TC58NYG2S3ETA00
Manufacturer Toshiba
File Size 500.42 KB
Description 4 GBIT (512M x 8 BIT) CMOS NAND E2PROM
Datasheet download datasheet TC58NYG2S3ETA00 Datasheet

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Full PDF Text Transcription (Reference)

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TC58NYG2S3ETA00 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 4 GBIT (512M × 8 BIT) CMOS NAND E2PROM DESCRIPTION The TC58NYG2S3E is a single 1.8V 4 Gbit (4,429,185,024 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 4096blocks. The device has two 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages). The TC58NYG2S3E is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.