Download SI4953ADY Datasheet PDF
SI4953ADY page 2
Page 2
SI4953ADY page 3
Page 3

SI4953ADY Description

The attached spice model describes the typical of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage.