CDCLVP111-EP Overview
The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines.
CDCLVP111-EP Key Features
- Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL
- Fully patible With LVECL and LVPECL
- Supports a Wide Supply Voltage Range From
- Selectable Clock Input Through CLK_SEL
- Low-Output Skew (Typ 15 ps) for Clock