DS90C3202 Datasheet | Texas Instruments

.ti. SNLS191D - APRIL 2005 - REVISED APRIL 2013 DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver Check for Samples: DS90C3202 Features - 2 Up to 9.45 Gbit/s data throughput - 8 MHz to 135 MHz input clock support - Supports up to QXGA panel resolutions - Supports HDTV panel resolutions and frame rates up to 1920 x 1080p - LVDS 30-bit, 24-bit or 18-bit color data inputs - Supports single pixel and dual pixel interfaces - Supports spread spectrum clocking - Two-wire serial munication interface - Programmable clock edge and control strobe select - Power down mode - +3.3V supply voltage - 128-pin TQFP Package - pliant to TIA/EIA-644-A-2001 LVDS Standard DESCRIPTION The DS90C3202 is a 3.3V single/dual FPD-Link 10bit color receiver is designed to be used in Liquid Crystal Display TVs, LCD Monitors, Digital TVs, and Plasma Display Panel TVs. The DS90C3202 is designed to interface between the digital video processor and the display device using the lowpower, low-EMI LVDS (Low Voltage Differential Signaling) interface. The DS90C3202 converts up to ten LVDS data streams back into 70 bits of parallel LVCMOS/LVTTL data. The receiver can be programmed with rising edge or falling edge clock. Optional wo-wire serial programming allows fine tuning in development and production environments. With an input clock at 135 MHz, the maximum transmission rate of each LVDS line is 945 Mbps, for an aggregate throughput rate of 9.45 Gbps (945 Mbytes/s). This allows the dual 10-bit LVDS Receiver to support resolutions up to HDTV. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard...