Overview: TMS320TCI100Q FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS251E − JUNE 2004 − REVISED JUNE 2006 D Highest-Performance Fixed-Point Digital − 8M-Bit (1024K-Byte) L2 Unified Mapped Signal Processors (DSPs) RAM/Cache (Flexible Allocation) − 1.18-ns Instruction Cycle Time − 850-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − Twenty-Eight Operations/Cycle − 6800 MIPS − Fully Software-patible With C62x − TCI100/C6416 Pin-patible − Extended Temperature Device Available
D VelociTI.2 Extensions to VelociTI
Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x DSP Core − Eight Highly Independent Functional
Units With VelociTI.2 Extensions: − Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle − Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle − Non-Aligned Load-Store Architecture − 64 32-Bit General-Purpose Registers D Two External Memory Interfaces (EMIFs)
− One 64-Bit (EMIFA), One 16-Bit (EMIFB) − Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) − 1280M-Byte Total Addressable External Memory Space
D Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
D Host-Port Interface (HPI)
− User-Configurable Bus Width (32-/16-Bit)
D 32-Bit/33-MHz, 3.3-V PCI Master/Slave
Interface Conforms to PCI Specification 2.
