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TMS320TCI6487 - DIGITAL SIGNAL PROCESSOR

General Description

The TMS320C64x+ DSPs (including the TMS320TCI6487/8 device) are the highest-performance communications infrastructure DSP generation in the TMS320C6000™ DSP platform.

Key Features

  • High-Performance Communications Infrastructure DSP (TCI6487/8).
  • 1-ns Instruction Cycle Time.
  • 1.0-GHz Clock Rate.
  • Eight 32-Bit Instructions/Cycle.
  • Commercial Temperature 0°C to 100°C.
  • 3 TMS320C64x+™ DSP Cores.
  • Dedicated SPLOOP Instructions.
  • Compact Instructions (16-Bit).
  • Exception Handling.
  • TMS320C64x+ Megamodule L1/L2 Memory Architecture.
  • 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped].

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Full PDF Text Transcription for TMS320TCI6487 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for TMS320TCI6487. For precise diagrams, and layout, please refer to the original PDF.

www.ti.com TMS320TCI6487 TMS320TCI6488 Communications Infrastructure Digital Signal Processor SPRS358F – APRIL 2007 – REVISED AUGUST 2008 1 Features • High-Performance Co...

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8F – APRIL 2007 – REVISED AUGUST 2008 1 Features • High-Performance Communications Infrastructure DSP (TCI6487/8) – 1-ns Instruction Cycle Time – 1.0-GHz Clock Rate – Eight 32-Bit Instructions/Cycle – Commercial Temperature 0°C to 100°C • 3 TMS320C64x+™ DSP Cores – Dedicated SPLOOP Instructions – Compact Instructions (16-Bit) – Exception Handling • TMS320C64x+ Megamodule L1/L2 Memory Architecture – 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped] – 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative] – 24 M-Bit (3072 K-Byte) Total L2 Unified Mapped RAM/Cache [Flexible Allocation] • Configurable at boot-time

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