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TMS320TCI6489 - DIGITAL SIGNAL PROCESSOR

General Description

The TMS320C64x+ DSPs (including the TMS320TCI6489 device) are the highest-performance communications infrastructure DSP generation in the TMS320C6000™ DSP platform.

Key Features

  • 12.
  • Key Features.
  • High-Performance Communications Infrastructure DSP (TCI6489).
  • 1.18-ns Instruction Cycle Time.
  • 850-MHz Clock Rate.
  • 0°C to 100°C Commercial Temperature.
  • 3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core).
  • One Receive Accelerator (RAC).
  • Enhanced VCP2/TCP2.
  • Frame Synchronization Interface.
  • 16-/32-Bit DDR2-667 Memory Controller.
  • EDMA3 Controller.
  • Antenna Inter.

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Full PDF Text Transcription for TMS320TCI6489 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for TMS320TCI6489. For precise diagrams, and layout, please refer to the original PDF.

TMS320TCI6489 www.ti.com SPRS626B – NOVEMBER 2009 – REVISED APRIL 2011 TMS320TCI6489 Communications Infrastructure Digital Signal Processor PRODUCT PREVIEW 1 Features 12 ...

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Infrastructure Digital Signal Processor PRODUCT PREVIEW 1 Features 12 • Key Features – High-Performance Communications Infrastructure DSP (TCI6489) – 1.18-ns Instruction Cycle Time – 850-MHz Clock Rate – 0°C to 100°C Commercial Temperature – 3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core) – One Receive Accelerator (RAC) – Enhanced VCP2/TCP2 – Frame Synchronization Interface – 16-/32-Bit DDR2-667 Memory Controller – EDMA3 Controller – Antenna Interface – One 1.8-V Inter-Integrated Circuit (I2C) Bus – Two 1.

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