HEF4027BT - Dual JK flip-flop

This page provides the datasheet information for the HEF4027BT, a member of the HEF4027B Dual JK flip-flop family.

Product Overview

nexperia

Datasheet Details

Part number	HEF4027BT
Manufacturer	nexperia
File Size	217.51 KB
Description	Dual JK flip-flop
Datasheet	HEF4027BT Datasheet
Additional preview pages of the HEF4027BT datasheet.

HEF4027BT Product details

Description

The HEF4027B is a dual positive-edge triggered JK flip-flop featuring independent set direct (nSD), clear direct (nCD), clock inputs (nCP) and complementary outputs (nQ and nQ).

Data is accepted when nCP is LOW, and transferred to the output on the positive-going edge of the clock.

Features

Wide supply voltage range from 3.0 V to 15.0 V.
CMOS low power dissipation.
High noise immunity.
Fully static operation.
5 V, 10 V, and 15 V parametric ratings.
Standardized symmetrical output characteristics.
Complies with JEDEC standard JESD 13-B.
ESD protection:.
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V.
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V.
Specified from -40 °C to +85.

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Published: Apr 18, 2025 |