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HEF4027BT - Dual JK flip-flop

Download the HEF4027BT datasheet PDF. This datasheet also covers the HEF4027B variant, as both devices belong to the same dual jk flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

The HEF4027B is a dual positive-edge triggered JK flip-flop featuring independent set direct (nSD), clear direct (nCD), clock inputs (nCP) and complementary outputs (nQ and nQ).

Data is accepted when nCP is LOW, and transferred to the output on the positive-going edge of the clock.

Key Features

  • Wide supply voltage range from 3.0 V to 15.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Fully static operation.
  • 5 V, 10 V, and 15 V parametric ratings.
  • Standardized symmetrical output characteristics.
  • Complies with JEDEC standard JESD 13-B.
  • ESD protection:.
  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V.
  • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V.
  • Specified from -40 °C to +85.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HEF4027B-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
HEF4027B Dual JK flip-flop NXP
HEF4027B-Q100 Dual JK flip-flop NXP
HEF4020B 14-stage binary counter NXP
HEF4021B 8-bit static shift register NXP
HEF4022B 4-stage divide-by-8 Johnson counter NXP

Other Datasheets by Nexperia

Part Number Description
HEF4027B Dual JK flip-flop
HEF4027B-Q100 Dual JK flip-flop
HEF4020B 14-stage binary counter
HEF4020B-Q100 14-stage binary counter
HEF4021B 8-bit static shift register

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HEF4027B Dual JK flip-flop Rev. 12 — 8 August 2024 Product data sheet 1. General description The HEF4027B is a dual positive-edge triggered JK flip-flop featuring independent set direct (nSD), clear direct (nCD), clock inputs (nCP) and complementary outputs (nQ and nQ). Data is accepted when nCP is LOW, and transferred to the output on the positive-going edge of the clock. The asynchronous clear-direct (nCD) and set-direct (nSD) are independent and override the nJ, nK, and nCP inputs. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. 2. Features and benefits • Wide supply voltage range from 3.