74LVC1G175 Datasheet
74LVC1G175 Datasheet (Nexperia)
Nexperia
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR.
and benefits
* Wide supply voltage range from 1.65 V to 5.5 V
* High noise immunity
* Overvoltage tolerant inputs to 5.5 V
* ±24 mA output drive (VCC = 3.0 V)
* CMOS low power dissipation
* Direct interface with TTL levels
* IOFF circuitry provides partial Power-down mode operation
* Latch-up perfor.
74LVC1G175 Datasheet (NXP Semiconductors)
NXP Semiconductors
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR.
and benefits
* Wide supply voltage range from 1.65 V to 5.5 V
* 5 V tolerant inputs for interfacing with 5 V logic
* High noise immunity
* Complies with JEDEC standard:
* JESD8-7 (1.65 V to 1.95 V)
* JESD8-5 (2.3 V to 2.7 V)
* JESD8B/JESD36 (2.7 V to 3.6 V).
* ESD protection:
* HBM JESD22-A114F exce.