| Part Number | 74LVC374A Datasheet |
|---|---|
| Manufacturer | NXP Semiconductors |
| Overview |
The 74LVC374A is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) ar.
allow the use of these devices as translators in mixed 3.3 V and 5 V applications.
The 74LVC374A is functionally identical to the 74LVC574A, but has a different pin arrangement.
2. Features and benefits
* 5 V tolerant inputs/outputs; for interfacing with 5 V logic * Wide supply voltage range from 1.. |
74LVC374A Datasheet and Specifications PDF
The 74LVC374A is a Octal D-type flip-flop.
| Part Number | 74LVC374A Datasheet |
|---|---|
| Description | Low-Voltage CMOS Octal D-Type Flip-Flop |
| Manufacturer | onsemi |
| Overview | 74LVC374A Low-Voltage CMOS Octal D-Type Flip-Flop With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74LVC374A is a high performance, non−inverting octal D−type flip−flop operating fro. . |
| Part Number | 74LVC374A Datasheet |
|---|---|
| Description | OCTAL D-TYPE FLIP-FLOP |
| Manufacturer | Diodes Incorporated |
| Overview |
The 74LVC374A provides eight edge-triggered D-type flip-flops featuring 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particu.
* Supply Voltage Range from 1.65V to 3.6V * Sinks or Sources 24ma at VCC = 3V * CMOS Low Power Consumption * IOFF Supports Partial Power Down Operation * Inputs or Outputs Accept Up to 5.5V * Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage Applications * Schmitt Trigger Action at All I. |
| Part Number | 74LVC374A Datasheet |
|---|---|
| Description | Octal D-type flip-flop |
| Manufacturer | Nexperia |
| Overview | The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their in. a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does . |