Datasheet4U Logo Datasheet4U.com

74LVC374A - Octal D-type flip-flop

General Description

The 74LVC374A is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications.

A clock input (CP) and an outputs enable input (OE) are common to all flip-flops.

Key Features

  • 5 V tolerant inputs/outputs; for interfacing with 5 V logic.
  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low power consumption.
  • Direct interface with TTL levels.
  • High-impedance when VCC = 0 V.
  • 8-bit positive edge-triggered register.
  • Independent register and 3-state buffer operation.
  • Complies with JEDEC standard:.
  • JESD8-7A (1.65 V to 1.95 V).
  • JESD8-5A (2.3 V to 2.7 V).
  • JESD8-C/JESD36 (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM J.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74LVC374A Octal D-type flip-flop nexperia
74LVC374A OCTAL D-TYPE FLIP-FLOP STMicroelectronics
74LVC374A OCTAL D-TYPE FLIP-FLOP Diodes
74LVC374A Low-Voltage CMOS Octal D-Type Flip-Flop ON Semiconductor
74LVC374A-Q100 Octal D-type flip-flop nexperia

Other Datasheets by NXP Semiconductors

Part Number Description
74LVC373A Octal D-type transparent latch
74LVC377 Octal D-type flip-flop
74LVC322244A 32-bit buffer/line driver
74LVC322245A 32-bit bus transceiver
74LVC32244A 32-bit buffer/line driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74LVC374A Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state Rev. 3 — 6 December 2012 Product data sheet 1. General description The 74LVC374A is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.