FDG6301N Datasheet and Specifications PDF

The FDG6301N is a Dual N-Channel Digital FET.

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Part NumberFDG6301N Datasheet
Manufactureronsemi
Overview These dual N−Channel logic level enhancement mode field effect transistors are produced using onsemi’s proprietary, high cell density, DMOS technology. This very high density process is especially tai.
* 25 V, 0.22 A Continuous, 0.65 A Peak  RDS(ON) = 4 W @ VGS = 4.5 V  RDS(ON) = 5 W @ VGS = 2.7 V
* Very Low Level Gate Drive Requirements Allowing Direct Operation in 3 V Circuits (VGS(th) < 1.5 V)
* Gate
*Source Zener for ESD Ruggedness (>6 kV Human Body Model)
* Compact Industry Standard SC70
*6 S.
Part NumberFDG6301N Datasheet
Description20V Dual N-Channel MOSFET
ManufacturerVBsemi
Overview FDG6301N-VB FDG6301N-VB Datasheet Dual N-Channel 20 V (D-S) MOSFET PRODUCT SUMMARY VDS (V) 20 RDS(on) (Ω) 0.086 at VGS = 4.5 V 0.110 at VGS = 2.5 V 0.180 at VGS = 1.8 V ID (A)a 2.
* Halogen-free According to IEC 61249-2-21 Definition
* Trench Power MOSFET
* 100 % Rg Tested
* Compliant to RoHS Directive 2002/95/EC APPLICATIONS SOT-363 SC-70
* Load Switch for Portable Applications D1 D2 S1 1 6 D1 G1 G2 G1 2 5 G2 D2 3 4 S2 Top View S1 S2 ABSOLUTE MAXIMUM RATINGS .
Part NumberFDG6301N Datasheet
DescriptionDual N-Channel MOSFET
ManufacturerKexin Semiconductor
Overview SMD Type Dual N-Channel MOSFET FDG6301N (KDG6301N) MOSFET ■ Features ● VDS (V) = 25V ● ID = 220m A (VGS = 4.5V) ● RDS(ON) < 4Ω (VGS = 4.5V) ● RDS(ON) < 5Ω (VGS = 2.7V) ● Gate-Source Zener for ESD r.
* VDS (V) = 25V
* ID = 220m A (VGS = 4.5V)
* RDS(ON) < 4Ω (VGS = 4.5V)
* RDS(ON) < 5Ω (VGS = 2.7V)
* Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). 1 or 4 6 or 3 2 or 5 5 or 2 3 or 6 4 or 1 1 S1 4 S2 2 G1 5 G2 3 D2 6 D1
* Absolute Maximum Ratings Ta = 25℃ Parameter Drain-Sou.
Part NumberFDG6301N Datasheet
DescriptionDual N-Channel/ Digital FET
ManufacturerFairchild Semiconductor
Overview These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially . 25 V, 0.22 A continuous, 0.65 A peak. RDS(ON) = 4 Ω @ VGS= 4.5 V, RDS(ON) = 5 Ω @ VGS= 2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). Compact industry standard SC70-6 surface mou.